1. Field of the Invention
This invention relates to semiconductor fabrication and more particularly to a high performance MOSFET with laterally reduced and/or relatively shallow source/drain regions.
2. Description of the Relevant Art
Fabrication of a MOSFET device is well known. Generally speaking, MOSFETs are manufactured by placing an undoped polycrystalline silicon (xe2x80x9cpolysiliconxe2x80x9d) material over a relatively thin gate oxide. The polysilicon material and the gate oxide are then patterned to form a gate conductor with source/drain regions adjacent to and on opposite sides of the gate conductor. The gate conductor and source/drain regions are then implanted with an impurity dopant species. If the impurity dopant species used for forming the source/drain regions is n-type, then the resulting MOSFET is an NMOSFET (xe2x80x9cn-channelxe2x80x9d) transistor device. Conversely, if the source/drain dopant species is p-type, then the resulting MOSFET is a PMOSFET (xe2x80x9cp-channelxe2x80x9d) transistor device. Integrated circuits utilize either n-channel devices exclusively, p-channel devices exclusively, or a combination of both on a single substrate. While both types of devices can be formed, the devices are distinguishable based on the dopant species used.
The operating characteristics of a MOSFET device are a function of the transistor""s dimensions. In particular, the drain current (Ids) is proportional to the ratio of the transistor""s channel width (W) to the transistor""s channel length (L) over a wide range of operating conditions. For a given transistor width and a given biasing condition (e.g., VG=3V, VD=3V, and VS=0V), Ids is maximized by minimizing the transistor""s channel length L. Minimizing channel length also improves the speed of integrated circuits which include a large number of individual transistors, since the larger drain currents characteristic of short channel devices may quickly drive the adjoining transistors into saturation. Minimizing L is, therefore, desirable from a device operation standpoint. In addition, minimizing the transistor length is desirable because a smaller area of silicon is required to manufacture a transistor having a smaller length. By minimizing the area required for a given transistor, the number of transistors available for a given area of silicon increases, and with it, a corresponding increase in the circuit complexity that can be achieved on the given area of silicon. Moreover, smaller transistors result in smaller die sizes. Smaller die sizes are desirable from a manufacturing perspective because they increase the number of devices that can be fabricated on a single silicon wafer and decrease the probability that any individual die is rendered inoperable during the fabrication process by randomly occurring defects that are caused by contaminating particles present in every fabrication facility.
As transistor length decreases below approximately 1.0 xcexcm, for example, a problem known as short channel effects becomes predominant. Generally speaking, short channel effects impact device operation by, inter alia, reducing device threshold voltages and increasing sub-threshold currents. As transistor length becomes small enough, the depletion regions associated with the junction areas may extend toward one another and substantially occupy the channel area. Hence, some of the channel will be partially depleted without any influence of gate voltage. Even at times when the gate voltage is below the threshold amount, current between the junctions (often referred to as subthreshold current) nonetheless exists for transistors having a relatively short transistor length.
A problem related to short channel effects, and the sub-threshold currents associated therewith, is the problem of hot-carrier effects. Hot carrier effects are a phenomenon by which hot-carriers (i.e., holes and electrons) arrive at or near an electric field gradient. The electric field gradient, often referred to as the maximum electric field (xe2x80x9cEmxe2x80x9d), occurs near the drain during saturated operation. More specifically, the electric field is predominant at the lateral junction of the drain adjacent to the channel. The electric field at the drain causes primarily electrons in the channel to gain kinetic energy and become xe2x80x9chotxe2x80x9d. These hot electrons traveling to the drain lose their energy by a process called impact ionization. Impact ionization serves to generate electron-hole pairs, wherein the pairs migrate to and become injected within the gate dielectric near the drain junction. Traps within the gate dielectric generally become electron traps, even if they are partially filled with holes. As a result, there is a net negative charge density in the gate dielectric. The trapped charge accumulates with time, resulting in a positive threshold shift in the NMOS transistor, or a negative threshold shift in a PMOS transistor. It is known that since hot electrons are more mobile than hot holes, hot carrier effects cause a greater threshold skew in NMOS transistors than PMOS transistors. Nonetheless, a PMOS transistor will undergo negative threshold skew if its transistor gate length is less than, e.g., 0.8 xcexcm.
Unless modifications are made to the process in which relatively small transistors are formed, problems with sub-threshold current and threshold shift resulting from short channel effects and hot carrier effects will remain. To overcome these problems, alternative drain structures such as double-diffused drains (xe2x80x9cDDDxe2x80x9d) and lightly doped drains (xe2x80x9cLDDxe2x80x9d) must be used. The purpose of both types of structures is the same: to absorb some of the potential into the drain and thus reduce Em. The popularity of DDD structures has given way to LDD structures, since DDD structures cause unacceptably deep junctions and deleterious junction capacitance.
A conventional LDD structure is one whereby a light concentration of impurity is self-aligned to the edge of the gate conductor. The light impurity concentration is then followed by a heavier impurity concentration which is self-aligned to a spacer formed on the sidewalls of the gate conductor. The purpose of the first implant dose is to produce a lightly doped section of both the source and drain junction areas at the gate edge near the channel. The second implant dose is spaced from the channel a distance dictated by the thickness of the sidewall spacer. Resulting from the first and second implants, an impurity gradient occurs across the junction from the source/drain area of the junction to the LDD area adjacent the channel.
The distance between the source and drain regions of a transistor is often referred to as the physical channel length. However, after implantation of dopant species into the source and drain regions and subsequent diffusion of the dopant species, the actual distance between the source and drain regions become less than the physical channel length, and is often referred to as the effective channel length (xe2x80x9cLeffxe2x80x9d). In VLSI designs, as the physical channel length becomes small, so too must the Leff. Decreasing the Leff of a transistor generally leads to an increase in short-channel effects in which the transistor""s properties, e.g., the transistor threshold voltage, undesirably vary from their design specification. Absent a comparable reduction in the depth of the source and drain junctions, the severity of the short channel effects resulting from a decrease in Leff may be profound. Accordingly, it has become necessary to scale down the vertical dimensions of the source and drain regions (i.e., the depth of the source/drain implant) to ensure proper operation of transistor devices.
The formation of shallow source and drain regions (i.e., junctions) is, however, rather difficult for PMOSFET devices which include boron-implanted junctions. Due to the relatively high diffusivity and channeling of boron atoms, implanted boron can penetrate deeply into the substrate. While using very low implant energies of boron might produce relatively shallow junctions, advances in technology are required to make available low-energy ion implanters before such low implant energies can be realized. Further, while reducing the junction depth provides protection against short channel effects, it also gives rise to increased resistivity of the source and drain junctions, adversely impacting the device operation. As a result of the increased resistivity, the saturation drive current and the overall speed of the transistor may drop. Moreover, forming contacts to relatively shallow junctions has several drawbacks. A contact layer which consumes the underlying source and drain junctions is often used during contact formation. For example, a refractory metal may be deposited across the source and drain junctions and heated to promote a reaction between the metal and the underlying silicon, thereby forming a low resistivity self-aligned silicide (i.e., salicide) upon the junctions. The silicide may completely consume the shallow junctions, penetrating into the substrate underneath the junctions, a phenomenon known as xe2x80x9cjunction spikingxe2x80x9d. Consequently, the junctions may exhibit large current leakage or become electrically shorted. Therefore, precautions must be taken to prevent excessive consumption, and hence junction spiking, of the shallow junctions during contact formation.
It is therefore desirable to develop a method for forming a transistor with relatively shallow effective source/drain junctions. Such a transistor would be less likely to experience short channel effects even if the channel possesses a relatively short physical channel length.
Additionally, further shrinking of the transistor gate length tends to make LDD and source/drain regions of a conventional transistor less effective. For example, shorter channel lengths typically require the source/drain length to also be reduced to minimize short channel effects. It is therefore further desirable to develop a method for forming a transistor which has reduced LDD and source/drain regions. Such a transistor may experience reduced short channel effects even if the channel possesses a relatively short physical channel length. Further, by minimizing the length of the LDD and source/drain regions, the number of transistors available for a given area of silicon may be increased, and with it, a corresponding increase in the circuit complexity that can be achieved on the given area of silicon.
The problems outlined above are in large part solved by the techniques hereof for forming a transistor having shallow effective source drain regions and/or laterally shortened source/drain regions.
In one embodiment, a semiconductor substrate, which includes a gate dielectric layer, a gate conductor layer, and a masking layer is provided. The masking layer is preferably patterned using optical lithography techniques such that photoresist material adjacent to the gate conductor region may be removed. Selective removal of the photoresist material preferably exposes portions of the polysilicon layer adjacent to the gate conductor. The formed masking structure preferably serves to mask etch access to the portions of the gate conductor layer which will later become the gate conductor of a transistor.
Portions of the gate conductor layer, the gate dielectric layer, and the silicon substrate, which are adjacent to the masking structure, are preferably removed. The gate conductor layer, the gate dielectric layer, and the silicon substrate may be removed using a single etching step or multiple etching steps. Etching of the silicon substrate forms a mesa which preferably extends above the silicon substrate. Etching is continued such that a distance between an upper surface of the mesa and an upper surface of the semiconductor substrate is preferably greater than a depth of a subsequently implanted source/drain region. By forming the mesa in this manner, the mesa is preferably made from the same material used for the semiconductor substrate. Preferably, both the semiconductor substrate and the silicon mesa are composed of single crystalline silicon.
Subsequent to forming the mesa, the lateral width of the masking structure is preferably reduced by an isotropic etch. The etch is preferably terminated after a select lateral amount of the masking structure is removed. The reduced width masking structure may then be used as a mask to further reduce the width of the gate conductor. The gate conductor is preferably etched by an anisotropic etch process down to the gate dielectric. As a result of this etching process, the lateral width of the gate conductor is reduced. The reduction of the lateral width of the gate conductor allows the formation of a transistor having a gate conductor, and therefore a channel length, which is less than the optical resolution of the photolithographic equipment. An advantage of this process is that the density of transistors in an integrated circuit may be increased by using these reduced width transistors.
The implantation of a first dopant distribution preferably forms LDD areas within the elevated mesa, adjacent to the gate conductor. The LDD areas are preferably aligned with the sidewalls of gate conductor and extend to the lateral boundary of the mesa. In this manner, the length of the LDD area may be controlled without the use of further masking steps or isolation structures. The control of the length of the LDD areas may help to reduce short channel effects.
After removal of the masking structure, a spacer material is preferably deposited across the entire semiconductor topography to form a conformal layer. The spacer material may be composed of silicon oxide, nitride, or oxynitride deposited from a CVD apparatus. After deposition, the spacer material preferably undergoes an anisotropic etch such that spacers are formed on the sidewalls of the gate conductor.
After formation of the spacers, source/drain regions are preferably formed in the mesa. The gate conductor and the spacers preferably serve to mask the source/drain implant from the channel region and the portion of the LDD areas under the spacers. The source/drain implant is preferably of the same dopant species as the LDD implant, albeit at a higher concentration and energy than the LDD implants. The spacers preferably serve to align the source/drain regions a spaced distance from the gate conductor. The source/drain regions preferably extend to a sidewall of mesa. In this manner, source/drain regions are formed which are substantially contained within the mesa.
After formation of the source/drain regions, a dielectric layer may be formed over the semiconductor substrate. The dielectric layer may be deposited from a CVD apparatus. The upper surface of the dielectric layer is preferably planarized (e.g., polished) such that a substantially planar dielectric layer is produced. The formed dielectric layer may serve to isolate transistors from each other. Thus, a series of transistors may be formed and isolated from each other without the use of standard isolation techniques (e.g., LOCOS or trench isolation).
In another embodiment, a trench is preferably formed by etching entirely through a masking layer formed upon a silicon-based substrate and partially through the substrate. A plasma etch technique may be employed to ensure that the lateral boundaries of the masking layer and the sidewalls of the trench are substantially vertical. A gate dielectric is formed upon the base and a portion of the sidewalls of the trench. The gate dielectric may, e.g., comprise thermally grown silicon dioxide. The masking layer may be a material through which ambient oxygen cannot significantly migrate. For example, the masking layer may be composed of silicon nitride arranged upon a pad oxide layer. The presence of such a masking layer upon the horizontal uppermost surface of the substrate may substantially inhibit the underlying silicon-based surface from being oxidized during the formation of the gate dielectric.
A dielectric layer (e.g., oxide) may be deposited by chemical-vapor deposition (xe2x80x9cCVDxe2x80x9d) across the masking layer and the gate dielectric such that a pair of dielectric sidewall spacers are formed laterally adjacent to sidewalls of the masking layer. Subsequently, a gate conductor material (e.g., polysilicon) may be deposited into the trench across the dielectric layer to a level spaced above the upper surface of the masking layer. Thereafter, the gate conductor material and the dielectric layer are preferably removed from above the masking layer such that the upper surface of the gate conductor material is substantially coplanar with the upper surface of the masking layer. The portion of the gate conductor material retained between the dielectric sidewall spacers serves as the gate conductor for an ensuing transistor.
The sidewall spacers may then be selectively etched to a level approximately commensurate with the lower surface of the gate conductor. In this manner, the opposed lateral boundaries of the masking layer and the opposed sidewall surfaces of the gate conductor are preferably exposed. The distance between a lower surface of the gate conductor and an upper surface of the semiconductor substrate may now be adjusted by etching the semiconductor substrate. Reduction of this distance serves to reduce the depth of the subsequently formed source/drain regions.
An LDD implant which is self-aligned to those exposed lateral boundaries of the masking layer and sidewall surfaces of the gate conductor may then be performed. Absent the pre-existing sidewall spacers, the LDD dopant species are preferably permitted to pass into the substrate to form LDD areas without using a high implant energy. The lateral width of each LDD area is preferably dictated by the lateral thickness of the sidewall spacer previously arranged directly above that LDD area. The dielectric layer may be thus conformally deposited across the relatively short lateral boundaries of the masking layer to form sidewall spacers of substantially uniform lateral thickness. The lateral edges of the sidewall spacers are thus parallel to the vertically rising lateral boundaries of the masking layer. The vertical orientation of the boundaries of the masking layer and the sidewall surfaces of the gate conductor preferably allow the size of the LDD areas to be dictated primarily by the thickness of the sidewall spacers interposed between the two surfaces.
Subsequent to performing the LDD implant, the masking layer is preferably removed from the substrate surface. A spacer layer composed of a dielectric, e.g., oxide, nitride, or silicon oxynitride, is then deposited upon over the semiconductor substrate. An anisotropic etch is preferably performed to remove portions of the dielectric layer on the horizontal surfaces of the substrate. The anisotropic etch permits relatively thin sidewall spacers to be formed adjacent to the gate conductor sidewalls. A source/drain implant which is self-aligned to exposed lateral edges of the spacers is forwarded into the substrate to a depth spaced below the base of the trench to form source and drain regions laterally adjacent to the LDD areas. The dielectric residing upon the upper surface of the gate conductor may then be removed using, e.g., an anisotropic etch. Self-aligned metal silicide (i.e., salicide) structures may be formed upon the source and drain regions and the upper surface of the gate conductor by heating a refractory metal deposited across the topography, thereby causing silicon to react with the metal. The presence of the dielectric sidewall structures may prevent the refractory metal from contacting and reacting with the polysilicon sidewall surfaces of the gate conductor. Thus, silicide shorting between the gate conductor and the source and drain regions may be less likely to occur.